The present invention relates to a circuit for controlling the storage of data into memory and in particular but not exclusively to a pulse generator. The memory may be a first-in-first-out (FIFO) memory array.
Reference is made to FIG. 1 which shows a known arrangement which has a first flip flop 2. The first flip flop 2 has a clock input 6 for receiving a clock signal clk. The first flip flop 2 also has an input 4 for receiving a decoded address adr dec out. That decoded address adr_dec_out is output via output 8 of the first flip flop 2 and provides a write enable signal. A second flip flop 9 also receives a clock signal clk via input 7 and the data to be written to a memory via input 11. The output 13 of the second flip flop 9 is input to a first inverter 10. The output of the first inverter 10 is input to a second inverter 12. A capacitor is provided between the output of the first inverter 10 and ground. The first and second inverters 10 and 12 and the capacitor 14 together constitute a delay element 15. In other words, the output of the second flip flop 9 is provided at the output of the second inverter 12 but a delayed time after it is input to the first inverter 10. The output of the second inverter 12 provides a data signal data_array_in to be written to a column of the memory array. If the write enable signal wr_ena is high, then the data data_array_in will be written into a memory cell contained in that column enabled by the write enable signal.
Reference is now made to FIGS. 2a to c. FIG. 2a shows the timing of the clock signal clk input to the first and second flip flops 2 and 9 for three clock cycles CYCLE 1-3. FIG. 2a shows a first scenario for the timing of the data from the second flip flip 9 to be written into the memory cells and the write enable signal from the first flip flop 2. As indicated by Reference A, the write enable signal is disabled well before the next data is received by the second flip flop. This next data is associated with a different write enable signal. FIG. 2c shows a second scenario where the write enable signal wr_en for first data is still enabled when the next data is received. This is indicated by reference B. When the write enable signal has the high level, data can be written into an appropriate location in the memory array.
As can be seen the data signal transitions and the write enable signal transitions occur more or less at the same time. This gives rise to the problem of shoot through effects. With shoot through effects, the wrong data may be written to the wrong memory cell. For example, with the second scenario shown in FIG. 2c the write enable signal for first data is still enabled when the next data is received. The wrong data may therefore be written into the wrong cell. This can occur if that write signal is high when the data from the previous cycle is available. Likewise, the data from the subsequent cycle intended for the cell in column nxe2x88x921 may be written into a memory cell in column n because the first write enable signal wr_ena is still enabled when the next bit of data for the cell in column nxe2x88x921 is received. Both of these scenarios are undesirable.
The delay element 15 is provided to attempt to deal with this problem. This delay element is provided so that the write enable signal is delayed with respect to the arrival time of the data signals. However, this arrangement has the disadvantage that the delay provided is dependent on the length of wires and position of the flip flops. Accordingly, it is difficult to accurately predict the delay that would be provided by the delay element 15 and this can cause difficulties.
If the delay element is not adjusted correctly, shoot-through effects might persist.
It is therefore an aim of embodiments of the present invention to address these problems.
According to one aspect of the present invention, there is provided a circuit for controlling the storage of data in a memory element, said circuit comprising a) a bistable device having a first input for receiving an address input and a second input for receiving a clock signal; and b) circuitry for receiving the output of the bistable device and the clock signal and providing a write enable signal for said memory, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, said first and next transitions being in the same clock cycle.
In this way, it can be ensured that the write enable signal is disabled well before the end of a given clock cycle.
Preferably, the duration of an enabled write enable signal is substantially the same as half a clock cycle.
Embodiments of the invention may be advantageous in that no special care needs to be taken to avoid xe2x80x9cshoot throughxe2x80x9d effects. The embodiments may inherently deal with this problem.
The bistable circuit may be a latch. This latch may be a D-latch.
The circuitry may comprise an AND gate or any other suitable circuitry.
The state of said write enable signal when enabled is dependent on the address of the first input when said clock signal is first enabled.
According to a second aspect of the present invention there is provided a write enable signal generator having a plurality of circuits as discussed hereinbefore, each of said circuits providing a write enable signal for a respective element of a memory array. That memory element may be a column or the like of the memory array.
According to a third aspect of the present invention, there is provided a memory arrangement comprising a generator as defined hereinbefore and a plurality of memory elements, said memory elements being equal in number to said circuits. The memory array may be a FIFO memory array or any other suitable memory array.